The present invention relates to testing semiconductor devices, and more particularly, to the use of automatic test equipment ("ATE") for predicting propagation delay.
Semiconductor devices, or integrated circuits, are susceptible to a wide variety of defects at all stages of their manufacture. Therefore, before semiconductor circuits are shipped to the consumer, they are tested. One tested parameter is propagation delay. The propagation delay generally refers to the time required for a signal to travel through a given circuit path and is particularly important in testing CMOS devices. Each semiconductor device contains a number of circuits which are tested in connection with their propagation delay. Unless the propagation delay falls within a certain acceptable range, the device is considered defective and is not shipped to the consumer.
Automatic test equipment useful for testing the propagation delay of a device is commercially available. Examples of useful equipment are the STS6120, STS8256, Vista LT and Vista Logic, all manufactured by Credence Systems Corporation. Other suitable ATE is also available, and additional examples will occur to those skilled in the art.
However, one problem encountered with all such automatic test equipment is that the equipment itself presents a capacitive load, especially to the output stages of the device being tested, which will affect the measurements made on the device. Therefore, it is necessary that the capacitive load presented by the ATE be taken into consideration when the result of the propagation delay measurements are analyzed.
In order to predict the effects of the capacitive load presented by the ATE on the device being tested, it is necessary to run computer simulations for the device with the same capacitive load as the tester in question placed on the output circuits of the device. Methods and equipment for running such simulations are known to those of skill in the art. However, for purposes of the present discussion, it is sufficient to state that running such a simulation is an expensive and time-consuming task.
The above-described problems are further compounded when it is considered that the capacitive load presented by the ATE varies from one tester to the next. Therefore, the test program generation for each ATE platform requires a separate simulation. This leads to production delays in testing semiconductor devices when a tester breaks down and another tester, for which no simulation has yet been made, must be used in its place, because testing must be halted until computer simulations are run for the device as loaded by the capacitance of the replacement tester.
Therefore, it is an object of the present invention to provide a solution to these, and other related problems in the art.